NANDRY Protocol

An Open Machine Fabrication Protocol on Solana#

Version: 0.1
Date: August 2026
NANDRY turns programs and compact AI models into deterministic digital machines. A creator launches a foundry and issues its transistor token. Builders acquire those transistors, design a circuit, compile it into canonical NAND and LATCH gates, and burn the exact material bill to tape out a permanent Machine PDA. Executors can reconstruct the same machine, run the same input, and submit verifiable execution records to Solana.

Whitepaper Scope#

This document specifies the complete NANDRY protocol: the market for transistor materials, the compiler and machine identity rules, the tapeout transaction, the execution network, and the Solana account model.

The protocol makes five objects economically and technically distinct:

• a Processor operates a transistor foundry;
• a Transistor is a fungible fabrication material;
• a Circuit is a canonical digital design;
• a Machine is a taped-out and permanently addressed circuit;
• an Execution is a verifiable run of that machine.

Users mint transistors. Tapeout creates machines.

1. Protocol Overview#

NANDRY connects a primary materials market to a deterministic machine compiler.

1. A creator opens a Processor foundry and fixes a name, symbol, maximum supply, and factory price.
2. Users mint the Processor's transistor token with SOL. Revenue settles directly to the foundry creator, while the protocol fee settles to the protocol treasury.
3. A builder creates a circuit manually, with Verilog, through Cursor, or by importing a supported neural model.
4. The compiler lowers the design to a canonical NAND/LATCH netlist and produces a bill of materials.
5. Tapeout burns the required transistor balance and creates a Machine PDA containing the author, manufacturer, netlist commitment, gate counts, ports, and execution counters.
6. Any executor can reconstruct the machine, run an input, and submit a result under the selected verification mode.

The transistor market is therefore coupled to actual machine fabrication. Circuit complexity creates measurable material demand, and every completed tapeout removes those materials permanently from supply.

2. Six Design Decisions#

2.1 Burn connects materials to machines#

Every NAND consumes one transistor unit. Every LATCH consumes four. Tapeout destroys the exact bill of materials in the same transaction that creates the Machine PDA.

2.2 Equal inputs must produce equal outputs#

Canonical bytecode, fixed integer semantics, normalized inputs, and explicit clock behavior make execution reproducible across independent implementations.

2.3 Topology defines machine identity#

Screen position, colors, and editor layout do not affect identity. Gate kinds, ports, connections, constants, state initialization, and compiler version do.

2.4 Executors rebuild machines independently#

The chain stores identity and commitments. Executors obtain the canonical artifact, verify its digest, and rebuild the machine without trusting the original author.

2.5 Three execution modes cover different scales#

Small machines execute directly on Solana. Medium machines use segmented execution with challengeable commitments. Large machines can submit succinct proofs over the same canonical semantics.

2.6 A new version creates a new identity#

A sealed machine never mutates. A changed netlist, weight set, compiler target, or state layout produces a new Machine PDA.

3. Core Protocol Objects#

3.1 Processor: foundry and issuer#

A Processor is the economic root of a NANDRY ecosystem. It records the creator, transistor Mint, supply cap, factory price, cumulative issuance, burned materials, machine count, execution count, and fee policy.

Before the first mint, its creator may correct the supply and factory price or close the foundry. The first successful mint permanently seals those economic parameters.

3.2 Transistor: fabrication material#

Each Processor controls one Token-2022 Mint. Its tokens are fungible, transferable, and consumable. They represent fabrication capacity inside that Processor ecosystem; they do not confer governance rights or ownership of the protocol.

3.3 Circuit: canonical digital design#

A Circuit contains typed input and output ports, NAND gates, LATCH state cells, constants, connections, optional modules, and compiler metadata. The compiler rejects undriven inputs, multiple drivers, illegal cycles, invalid ports, and unsupported state transitions.

3.4 Model: neural definition#

A supported model contains fixed integer or binary weights, thresholds, layer shapes, activation rules, input normalization, output labels, and a compiler target. Model registration commits to the model artifact and the circuit produced from it.

3.5 Machine: completed tapeout#

A Machine PDA is the permanent onchain identity of a fabricated circuit. It records:

• machine author and manufacturer;
• parent Processor and transistor Mint;
• canonical netlist hash;
• input/output schema;
• NAND and LATCH counts;
• compiler and virtual-machine versions;
• artifact commitment and availability metadata;
• total materials burned;
• run count and finalization status.

3.6 Execution: job and receipt#

An execution request binds a Machine PDA, normalized input, verification mode, reward, deadline, and replay domain. A MachineRun records the output commitment, trace root or proof, executor, slot, and settlement state.

4. Machine Fabrication Lifecycle#

4.1 Open a Processor foundry#

The creator signs a create_processor instruction. The protocol creates the Processor PDA and its Token-2022 Mint with protocol-controlled mint authority and no freeze authority.

4.2 Acquire transistors#

Users mint directly from the foundry or fill an existing SOL bid. Factory mint revenue is paid to the creator. No hidden creator allocation is created at launch.

4.3 Design and compile#

The Machine Workshop accepts canvas circuits, Verilog source, Cursor workspaces, and supported model artifacts. All paths converge on the same Circuit IR and deterministic compiler.

4.4 Tape out a Machine#

The builder signs one tapeout transaction. The protocol verifies the netlist commitment and material bill, burns the required transistor balance, and creates the Machine PDA atomically.

4.5 Execute the Machine#

An execution request supplies normalized input and a verification mode. Executors reproduce the canonical semantics, then submit a result, trace commitment, or proof.

5. Transistor Issuance and Burn#

5.1 One Processor, one Mint#

Every Processor issues one transistor token. A single material market avoids fragmented NAND/LATCH liquidity while the protocol still prices sequential state correctly through a fixed four-to-one LATCH weight.

5.2 Burn never restores issuance capacity#

The supply cap limits cumulative factory issuance. Burning transistors during tapeout does not reopen mint capacity. This preserves the original scarcity schedule.

5.3 Parameters seal after the first mint#

Supply and factory price remain editable only while cumulative issuance is zero. The first mint sets the lock bit permanently.

5.4 Creator allocation starts at zero#

Foundry creators receive revenue from factory sales, not an undisclosed token reserve. If a creator wants inventory, the acquisition is visible under the same rules as every other buyer.

5.5 Atomic factory settlement#

A factory mint calculates the sale amount and protocol fee, transfers SOL to the creator and treasury, and mints the requested transistor quantity in one atomic transaction.

6. Bid-Only Secondary Market#

NANDRY uses a one-sided order book. Buyers escrow SOL and publish bids. Sellers fill those bids with transistor tokens. There is no separate ask listing surface.

6.1 Escrowed SOL bids#

A bid stores the Processor, buyer, price, remaining quantity, escrow balance, nonce, and status. The full purchase capacity is funded at creation.

6.2 Bid fills#

A fill transfers transistor tokens from seller to buyer, pays SOL from escrow to the seller, routes the protocol trade fee, and decreases the remaining quantity.

6.3 Bid cancellation#

Only the buyer can cancel an open bid. Unused escrow returns to that buyer.

6.4 Market signals#

The product reports factory price, highest live bid, bid depth, circulating supply, market value, burned materials, taped-out machines, and real execution count. Utility is visible beside price.

7. Machine Workshop#

7.1 Four design paths#

Builders can wire gates manually, write Verilog, develop through Cursor, or import a supported neural model. Each path produces the same typed Circuit IR.

7.2 Deterministic compiler pipeline#

The compiler parses, elaborates modules, validates ports, lowers operators, maps logic to NAND, inserts LATCH state, canonicalizes identifiers, performs static timing analysis, and emits canonical bytecode plus a manifest.

7.3 Automatic wiring and hierarchy#

The editor uses semantic ports rather than decorative lines. Connections remain attached while nodes move. Larger modules can collapse into hierarchical blocks without changing netlist identity.

7.4 Reproducible builds#

The compiler version, target VM version, optimization profile, and source commitments are included in the build manifest. Independent builders must derive the same canonical digest.

8. Compiling Models into Machines#

8.1 Binary neural networks#

Binary weights and activations replace multiplication with XNOR and population count. A neuron evaluates bit matches, sums them through an adder tree, compares the score with a fixed threshold, and optionally stores the activation in a LATCH.

8.2 Binary CNN compilation#

Convolution is lowered into repeated binary dot products over fixed windows. Weight sharing remains explicit in the model artifact, while the canonical circuit defines the exact execution schedule and state reuse.

8.3 Model ID#

The Model ID commits to architecture, weights, thresholds, normalization, labels, compiler target, and version. Two identical model artifacts produce the same Model ID.

8.4 Model sealing#

After sealing, weights and compiler semantics cannot change under that identity. Upgrades publish a new model and a new Machine PDA.

8.5 Verifiable inference visualization#

The Neural Fabric view maps inputs, weight paths, population-count stages, thresholds, activations, clock boundaries, and outputs to the canonical execution trace. The animation is generated from machine state rather than a fabricated chain-of-thought narrative.

9. Canonical Circuit and Virtual Machine#

9.1 NAND and LATCH primitives#

NAND supplies universal combinational logic. LATCH supplies one tick of persistent state. All supported machines reduce to these two primitives plus explicit ports and constants.

9.2 Canonical bytecode#

The minimum instruction set defines inputs, constants, NAND nodes, LATCH nodes, outputs, modules, and connection records. Integer fields use fixed widths and canonical endianness.

9.3 Structural constraints#

The compiler enforces unique drivers, valid topological ordering for combinational paths, explicit sequential feedback, bounded fan-out representation, and complete output driving.

9.4 Tick semantics#

During a tick, combinational gates evaluate from the current input and prior state. Output ports are committed. LATCH next-state values then replace current state at the clock boundary.

9.5 Gate-level accounting#

The tapeout manifest reports NAND count, LATCH count, critical path, bytecode length, and material burn. The protocol bill is NAND + 4 × LATCH transistor units.

10. Tapeout and Machine PDA#

10.1 Pre-tapeout validation#

The protocol verifies ownership, compiler compatibility, artifact commitment, gate counts, ports, material bill, and sufficient transistor balance.

10.2 Atomic burn and creation#

The tapeout instruction burns transistor tokens and initializes the Machine PDA in one transaction. A failed machine creation cannot leave a successful material burn behind.

10.3 Address derivation#

Machine addresses are derived from a domain tag, Processor address, canonical netlist hash, author, and version nonce. Collision checks occur before initialization.

10.4 Author and manufacturer#

The author signs the design identity. The manufacturer pays the material bill and submits tapeout. They may be the same wallet or different wallets.

11. Open Execution Network#

11.1 Mode A: direct onchain execution#

Small machines execute entirely inside a Solana instruction. The program loads canonical state, evaluates the bounded circuit, records the output, and settles the reward.

11.2 Mode B: segmented optimistic execution#

Medium machines split execution into deterministic segments. Executors post trace roots and checkpoints. Challengers can isolate a disputed segment for onchain replay.

11.3 Mode C: zero-knowledge execution proof#

Large machines may produce a succinct proof over the canonical VM. The public inputs bind the Machine PDA, machine version, normalized input, output, and execution domain.

11.4 Permissionless jobs#

Any wallet can post a job with a Machine PDA and SOL reward. Any compatible executor can compete. Verification and settlement follow the selected mode.

11.5 MachineRun#

Every accepted run creates or updates a MachineRun receipt with the request, executor, result commitment, trace or proof, slot, and payment status.

12. Solana Account Architecture#

The core accounts are ProtocolConfig, Processor, Bid, CircuitChunk, Model, Machine, ExecutionRequest, MachineRun, and optional challenge accounts.

12.1 PDA derivation#

Every account family uses a separate domain seed. Version fields are explicit, and variable-size identities are hashed before PDA derivation.

12.2 Large netlist accounts#

Large artifacts are uploaded in ordered chunks. Each chunk commits to its index and payload. Finalization verifies the complete artifact digest before it can be referenced by a Machine.

12.3 Finalization and immutability#

Processors seal their economics after first mint. Models and Machines seal when finalized. Mutable operational counters remain separate from immutable identity fields.

13. Distributed Artifact Storage#

Solana stores machine identity, commitments, economic state, and receipts. Canonical artifacts can be mirrored across content-addressed storage and executor nodes.

An artifact manifest includes the content digest, length, codec, chunk map, mirror list, and availability attestations. Executors verify bytes against the onchain digest before execution. No mirror can silently replace a machine.

14. Deterministic Execution and Verification#

14.1 Domain separation#

Model IDs, netlist hashes, execution inputs, trace leaves, and output commitments use distinct domain tags.

14.2 Input normalization#

Input length, bit order, numeric width, padding, and preprocessing are part of the Machine schema.

14.3 Output normalization#

Output ports, ordering, labels, and digest encoding are fixed by the Machine version.

14.4 Execution trace root#

Each step commits to the clock, instruction or gate range, input slice, prior state root, next state root, and output fragment. A Merkle root summarizes the complete run.

14.5 Cross-implementation consistency#

The protocol publishes conformance vectors for compilers, virtual machines, and proof systems. A release is compatible only when it reproduces the canonical digests and outputs.

15. Product Surfaces#

Market#

Discover transistor foundries, compare factory price and live bids, open a token detail page, mint materials, and trade through the bid-only order book.

Foundry#

Create a Processor, choose its brand, symbol, supply, factory price, and story, then receive revenue from primary transistor issuance.

Machine Workshop#

Design manually or through Verilog, Cursor, and model imports; compile to NAND/LATCH; inspect timing; and tape out a machine.

Execution Network#

Post SOL rewards, run canonical machines, submit verifiable results, and settle successful execution.

My Lab#

Manage transistor balances, created foundries, authored machines, manufactured machines, open jobs, execution receipts, and earnings.

16. Model Training and Machine Inference#

Training occurs offchain using conventional tools. NANDRY accepts a finalized, quantized model and manufactures its deterministic inference circuit. The protocol's job begins at model commitment: it fixes the weights and semantics, compiles the machine, records its material cost, and verifies execution.

This division keeps expensive optimization outside consensus while making deployed inference reproducible and independently executable.

17. Versioning and Extension Rules#

v1 Machine Standard#

NANDRY v1 includes Processor foundries, Token-2022 transistor issuance, primary mint settlement, bid-only trading, deterministic Circuit IR, NAND/LATCH compilation, atomic tapeout, Machine PDA registration, direct execution for bounded machines, and machine-readable protocol documentation.

Extension Boundary#

Segmented execution, formal challenge games, zero-knowledge proofs, broader HDL support, additional quantized model formats, artifact availability markets, and cross-chain verification use explicit version numbers and Program IDs. Every extension preserves the original machine identity rules.

18. Conclusion#

NANDRY gives digital machines an open manufacturing stack.

A foundry issues materials. A builder turns source code or a model into a canonical gate network. Tapeout burns the bill of materials and creates a permanent machine identity. Executors reproduce that machine and compete to run it. Solana records ownership, commitments, verification, and settlement.

The result is a market where computation can be issued, built, owned, inspected, executed, and paid for under one deterministic protocol.

Appendix A: Core Invariants#

1. One Processor controls exactly one transistor Mint.
2. Creator allocation is zero at foundry creation.
3. Supply and factory price seal after the first successful mint.
4. Burned transistors never restore cumulative issuance capacity.
5. Tapeout burn and Machine creation are atomic.
6. A sealed machine's identity fields never change.
7. The same canonical machine, state, and input produce the same output.
8. Execution rewards settle only after the selected verification rule succeeds.

Appendix B: Core Addresses#

Production deployments publish the Protocol program ID, protocol treasury, compiler release digest, supported VM versions, and verified artifact mirrors in the onchain ProtocolConfig and the public deployment manifest.

Appendix C: Terms#

Foundry: A Processor and its primary transistor issuance surface.
Transistor: Fungible fabrication material issued by a Processor.
Circuit IR: Typed intermediate representation shared by all design paths.
Tapeout: Atomic material burn and Machine PDA creation.
Machine: A finalized canonical circuit with permanent identity.
MachineRun: An accepted execution receipt.
Canonical artifact: The exact bytes whose digest defines build and execution behavior.
Execution mode: The verification path used for a machine run.